The present invention relates to an output buffer through which data are outputted externally, and more particularly to a data output buffer used in a semiconductor memory device formed as an integrated circuit device.
A semiconductor memory device has a plurality of memory cells, and a predetermined cell or cells are selected by an address decoder in response to address signals. The data stored in the selected memory cell or cells are amplified by a sense amplifier, and then read out to an external data bus through an output buffer. The output buffer includes first and second insulated gate field effect transistors (IGFETs) such as MOS (metal-oxide-semiconductor) transistors connected in series between first and second power supply terminals. The first power supply terminal may be supplied with a positive or negative power potential, and the second power supply terminal may be supplied with a reference potential such as a ground potential. The connection point of the first and second transistors is derived as a data output terminal which is in turn connected to an external data bus. The first and second transistors are supplied at their gates with the true and complementary outputs of the sense amplifier, respectively. Accordingly, either one of the first and second transistors is turned ON in response to the data stored in the selected memory cell, and the data output terminal takes a high level or a low level.
The output buffer further includes third and fourth IGFETs supplied with an output control signal. The third transistor is connected between the gate of the first transistor and the second power supply terminal, and the fourth transistor is connected between the gate of the second transistor and the second power supply terminal. When the third and fourth transistors are turn ON, the potentials at the gates of the first and second transistors are clamped to the level at the second power supply terminal. The first and second transistors are thereby turned OFF to bring the data output terminal into a high impedance state. As a result, the data stored in the memory cells are not read out, and the external data bus can transfer the data read out from another memory device, for example.
When the output control signal disappears, the third and fourth transistors are turned OFF to activate the output buffer. At least one memory cell is thereafter selected, and the data stored therein is supplied to the sense amplifier. The sense amplifier responds to the data supplied, and produces the true and complementary outputs thereof. The first transistor or the second transistor is thus turned ON. The data bus line connected to the data output terminal can be regarded as a capacitive load having a relatively large capacitance value. Accordingly, the capacitive load is charged through the first transistor by a charging current from the first power supply terminal, or is discharged by the second transistor, the discharging current flowing into the second power supply terminal. The sense amplifier holds the true and complementary outputs until another memory cell is selected or the output control signal is generated. When another memory cell is selected, the sense amplifier produces true and complementary outputs corresponding to the data stored in the newly selected memory cell. If the complementary output is thereby changed from the low level to the high level, the second transistor is turned ON to discharge the capacitive load connected to the data output terminal. On the other hand, the first transistor is turned OFF.
In order to read out the data stored in the selected memory cell to the data output terminal at a high speed, the sense amplifier performs the change in levels of its true and complementary outputs for a very short time to quickly turn one of the first and second transistors ON and the other of them OFF, respectively. In other words, the charging and discharging of the capacitive loads are attained within a considerably short time. Such rapid charging and discharging cooperate with the impedance and inductance components of power supply lines to cause an inductive noise at the first and second power supply terminals. In particular, the potential at the second power supply terminal is used as a reference potential for the high and low levels, and therefore, the inductive noise at the second power supply terminal pulls up the reference potential to bring the memory device into a read operation. The inductive noise may be suppressed by making the charging and discharging times long, but in that case the data read-out speed becomes slow.